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DC offset rejection in a frequencyfixed secondorder generalized integratorbased phaselocked loop for singlephase gridconnected applications
Protection and Control of Modern Power Systems volume 7, Article number: 1 (2022)
Abstract
Fast and accurate monitoring of the phase, amplitude, and frequency of the grid voltage is essential for singlephase gridconnected converters. The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closedloop stability of the gridconnected converters. In this paper, a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation (ADSC) in a secondorder generalized integrator (SOGI) phaselocked loop (PLL). A frequencyfixed SOGIbased PLL (FFSOGIPLL) is adopted to ensure better stability and to reduce the complexity compared with other SOGIbased PLLs. A smallsignal model of the proposed PLL is derived for the systematic design of proportionalintegral (PI) controller gains. The effects of frequency variation and ADSC on the proposed PLL are considered, and correction methods are adopted to accurately estimate grid information. The simulation results are presented, along with comparisons to other singlephase PLLs in terms of settling time, peak frequency, and phase error to validate the proposed PLL. The dynamic performance of the proposed PLL is also experimentally validated. Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices, offering an improved solution for precise grid synchronization in singlephase applications.
1 Introduction
Renewable energy sources are integrated into the grid using gridsynchronized voltage source converters. A precise grid synchronization algorithm influences the power, quality, and reliability of the grid. However, many issues must be overcome to avoid synchronizationrelated problems. The presence of DC offset in the grid voltage is considered a significant problem, affecting the operation of gridconnected converters and power quality [1,2,3].
Voltage and current sensors, signal conditioning circuits, quantification errors in the analogtodigitalconversion process, the mismatch of power semiconductor parameters, and current circulating between inverters are considered the major causes of DC offset in grid voltage [2,3,4,5,6,7,8,9,10]. The presence of DC offset not only deteriorates the performance of grid synchronization units but also affects the closedloop stability of gridconnected converters because of oscillations in the estimated grid frequency, phase, and voltage amplitude [2,3,4].
Much published research is related to orthogonal signal generation (OSG) methods used with singlephase phaselocked loops (PLLs) to create fictitious quadrature signals. Among the many reported OSGbased PLLs, the secondorder generalized integrator (SOGI) PLL has become the most popular for singlephase applications because of its low computation burden, straightforward implementation, and high filtering capability for loworder harmonics [1,2,3,4, 11, 12].
The SOGIPLL uses an OSG block to generate orthogonal signals from the singlephase grid voltage [2]; to implement the synchronization function, these are fed to the synchronous reference framebased PLL (SRFPLL) [13]. To ensure the accurate detection of frequency, voltage amplitude, and phase angle, the estimated SRFPLL frequency is fed back to the SOGI block, making the SOGIPLL frequency adaptive. However, this feedback increases the complexity of the design, and the design of loop filter gains becomes difficult [14].
Several SOGIbased PLLs have been reviewed in terms of their ability to remove the effect of DC offset from the grid synchronization process [4, 7]. These methods include the cascaded SOGIPLL, modified SOGIPLL, αβDSC_{2} with SOGIPLL, inloop dqframe DSC, complexcoefficient filter, notch filter, and moving average filterbased SOGIPLL. The αβDSC_{2}, SOGIPLL, and modified SOGIPLL have the shortest settling time when removing DC offset compared with the other SOGIPLLs. However, all these PLLs have a slow dynamic response, and the closedloop transfer function is of the thirdorder, which complicates controller design.
Reference [6] proposes a cascaded generalized integrator (CGI)based PLL consisting of two cascaded SOGI blocks. To reject DC offset, an SRFPLL adopting a frequencyfixed procedure is used to ensure stability and simple implementation. The two parameters that must be carefully adjusted to avoid affecting the PLL’s transient performance and harmonic filtering capability are designed to minimize the overall settling time of the PLL. However, because CGIPLL suffers from attenuation to loworder harmonics, the SRFPLL bandwidth must also be carefully selected to avoid unbalancing the quadrature signals. Also, using two SOGI blocks in a cascade to remove DC offset increases the system’s complexity. In [15], a dual SOGI and moving average filter inloop with the SRFPLL are combined to form a hybrid filterbased PLL. This method blocks the fundamental frequency negative sequence component, DC offset, and dominant harmonic components and has a relatively fast transient response. However, the transient response performance depends on the window length of the hybrid filter.
A mixed secondand thirdorder generalized integrator (MSTOGI)based PLL is presented in [16, 17]; it contains an extra branch to the SOGI block to eliminate DC offset and highfrequency harmonics from input signals. The MSTOGI gain affects the filtering capability, dynamic performance, and bandwidth of the SRFPLL. Therefore, the MSTOGIPLL controller gain has to match the MSTOGI gain to maintain stability and optimize the settling time. The dynamic performance of the MSTOGIPLL is proportional to its bandwidth, so a high bandwidth must be chosen to achieve a faster transient response. However, a higher bandwidth weakens the ability to suppress lowfrequency harmonics in the grid voltage. The system stability and pole trajectory aspects of generalized SOGI and TOGIbased PLLs have been investigated in [18]. Although a TOGI has advantages over a SOGI under harmonically distorted grid conditions, it is more complicated than a SOGI.
In [19], a frequencylocked loop (FLL) control method is used to eliminate DC offset, in which the FLL controller is combined with a modified SOGI block to estimate and obliterate DC offset from grid voltage. In general, since frequency adaptation is highly nonlinear, the linear control analysis technique cannot be directly applied, and thus it increases the design complexity. Also, the dynamic response of the SOGIFLL depends on the adequate selection of the FLL and SOGI gains. The complexity and computational burden of frequencyfixed SOGIbased PLL (FFSOGIPLL) is notably reduced compared with the classical SOGIPLL. This allows for higher bandwidth, better stability margin, and faster dynamic response. However, with grid frequency variation, FFSOGIPLL suffers from doublefrequency harmonics related to bandwidth selection [20].
The SOGIFLL with fixed frequency proposed in [21] incorporates a low pass filter with notch characteristics and a linearized phase error compensation to mitigate the doublefrequency oscillation in the estimated grid information. Although this FLL has straightforward parameter tuning and selective harmonic rejection capability based on a linearized phaseloop transfer function, it has limited DC offset rejection capability. In [22], a solution is proposed for the doublefrequency term and offset error in the frequencyfixed SOGI using a conformal mappingbased fractionalorder approach. The PLL shows good dynamic performance during different disturbances, including DC offset, by adjusting the fractionalorder gain according to grid frequency variations. However, the use of fractionalorder calculus increases system complexity and computational burden. A discretetime nonadaptive SOGIFLL based on a gradient descent algorithm is presented in [23]. Although its dynamic performance is smooth and fast, the method cannot completely reject DC offset.
A type 3 modified SOGIPLL is presented in [24], addressing the slow dynamic response, instability under voltage sag, and poor damping under other abnormal grid conditions by enhancing the gain and phase margins using gain and phaselead compensators. This PLL converges within two grid cycles under frequency, phase, and voltage sag disturbance. However, it cannot reject the DC offset. A modified version has been presented in [25] to add a DC offset rejection capability to the PLL using the notch filter. A tradeoff between the filtering capability and dynamic performance is recommended in assigning the SOGIPLL parameters. In addition, the design of the loop filter gains becomes difficult since the overall transfer function is of a high order. An enhanced structure SOGIPLL (ESOGIPLL) is proposed in [26]. This has a simple design and adequate performance when exposed to high DC offset values. However, the gain of the ESOGIPLL should be selected carefully so that it does not deteriorate the transient response and harmonic attenuation capability.
Two types of PLLs combining an openloop frequencyestimator and SOGI block are introduced in [27] using different normalization schemes to remove the dependency of the frequency estimator on grid frequency or phase angle information. The DC offset is canceled using an extra integrator added to the SOGI block to provide accurate grid information estimation with four grid cycles convergence speed. The computation burden of this PLL is reduced using a thirdorder polynomial approximation to implement the arctangent function, but this comes at the cost of accuracy. Reference [28] discusses many PLLs and FLLs, though most PLLs are either for threephase systems or based on openloop PLL structures. The openloop PLL is beyond the scope of this paper, while because of a lack of signal orthogonality, the design of a singlephase PLL is more challenging than that for threephase systems.
This paper presents a new method for removing the DC offset effect from a grid synchronization unit using arbitrarily delayed signal cancelation (ADSC) in a SOGIPLL. A frequencyfixed procedure is adopted to ensure stability and reduced complexity compared with other SOGIbased PLLs. Unlike other PLLs that rely on a SOGI, the proposed PLL can be accurately represented by a dominant secondorder system, making the loop filter design process straightforward. Moreover, the DC offset rejection capability of the proposed method is not restricted to a specific time delay. This gives the proposed PLL more flexibility than other related PLLs. A smallsignal model of the proposed PLL is derived for the systematic design of proportionalintegral (PI) controller gains. The effects of frequency variations and ADSC on the proposed PLL are considered, and phase and voltage amplitude correction methods are adopted to accurately estimate grid information.
The rest of the paper is organized as follows: Sect. 2 introduces the proposed method, including the required mathematical justifications, the smallsignal model, and the PIcontroller gain design. Numerical simulations are presented in Sect. 3 to verify and justify the derived smallsignal model. Experimental results compared with other related PLLs under different case studies are discussed in Sect. 4, and Sect. 5 concludes the paper.
2 Proposed method
Figure 1 presents the proposed FFSOGIPLL, which adopts a fixedfrequency concept to reduce implementation complexity, enhance relative stability, and simplify the control design following the recommendations in [14]. As shown in Fig. 1, an ADSC operator is used to cancel the DC offset from the orthogonal signals, v_{i} is the grid voltage, ω_{n} is the nominal grid frequency, and \({\widehat{\omega }}_{g}\) and \(\widehat{\theta }\) are the estimated grid frequency and phase angle, respectively. τ is the delay length of the ADSC, and k is the SOGI block gain factor. As shown in Fig. 1, the estimated frequency from the SRFPLL is fed back to the SOGI block to make it frequency adaptive.
The transfer functions of the fixedfrequency SOGI block, as shown in Fig. 1, are:
Assuming a grid voltage of \({v}_{i}\left(t\right)=V\mathrm{sin}\left({\omega }_{g}t\right)\), where V is the voltage amplitude and it is assumed to be 1 pu for simplicity, the Laplace transform for the grid voltage is obtained as:
The output voltage in the sdomain of the SOGI, assuming fixed frequency for a given input voltage, is written as:
Simplifying the partial fraction expansion, the time domain αβsignals \({v}_{\alpha }\left(t\right)\) and \({v}_{\beta }\left(t\right)\) are obtained as:
where \(\delta \) is the phase offset error, \(\mathrm{sin}\left(\delta \right)=\frac{{{\omega }_{g}}^{2}{{\omega }_{n}}^{2}}{\sqrt{{({{\omega }_{n}}^{2}{{\omega }_{g}}^{2})}^{2}+{k}^{2}{{\omega }_{n}}^{2}{{\omega }_{g}}^{2}}}\), \(A\), \(B\), \({\varphi }_{1}\), \({\varphi }_{2}\), and \({\omega }_{d}\) are functions of \({\omega }_{g}\), \({\omega }_{n}\), and \(k\).
From (6) and (7), it can be seen that \({v}_{\alpha }\left(t\right)\) and \({v}_{\beta }\left(t\right)\) have different amplitudes if \({\omega }_{g}\ne {\omega }_{n}.\) As \(\left{{\omega }_{n}}^{2}{{\widehat{\omega }}_{g}}^{2}\right\ll k{\omega }_{n}{\omega }_{g}\), (6) and (7) can be simplified as:
From (8) and (9), the \({v}_{\alpha }\left(t\right)\) amplitude is equal to 1, while the \({v}_{\beta }\left(t\right)\) amplitude is scaled by \({\omega }_{n}/{\omega }_{g}\). The signals after the ADSC operator are given as:
Substituting (8) and (9) into (10) and (11) yields:
where \(D\left(t\right)=A\left(\mathrm{sin}\left({\omega }_{d}t+{\varphi }_{1}\right)\mathrm{sin}\left({\omega }_{d}t+{\varphi }_{1}{\omega }_{d}\tau \right)\right){e}^{\frac{k{\omega }_{n}}{2}\tau }\).
where \(Q\left(t\right)=B\left(\mathrm{cos}\left({\omega }_{d}t+{\varphi }_{1}\right)\mathrm{cos}\left({\omega }_{d}t+{\varphi }_{1}{\omega }_{d}\tau \right)\right){e}^{\frac{k{\omega }_{n}}{2}\tau }\).
The terms \(D\left(t\right)\) and \(Q(t)\) decay to zero with the time constant \({\tau }_{p}=2/k{\omega }_{n}\). Therefore, (12) and (13) are simplified as:
where \(\theta ={\omega }_{g}t\). Using a fixed frequency in the SOGI block, \({v}_{\alpha }\left(t\right)\) is the orthogonal signal to \({v}_{\beta }\left(t\right){\widehat{\omega }}_{g}/{\omega }_{g}\) in the frequencylocked state (\({\omega }_{g}={\widehat{\omega }}_{g}\)). Hence, any variation in the grid frequency will result in a small phase difference \(\delta \) between the actual phase angle \(\theta \) and that of \({v}_{\alpha }\left(t\right)\).
If \({\theta }^{*}\) is the net phase angle difference at the grid side and \({\theta }^{*}=\theta \delta \), the transfer function of the SOGI block can be written as:
Equations (14) and (15) can be expressed using \({\theta }^{*}\) as:
Using ADSC to reject the DC offset will cause a phase error, so a phase correction of \({\theta }_{0}=\frac{{\widehat{\omega }}_{g}\tau }{2}\) is needed [9, 29]. The \({v}_{q}\left(t\right)\) signal with the phase correction can be obtained as:
which can be simplified to:
2.1 PLL smallsignal model
In this section, a smallsignal model for the proposed PLL is derived. The term \(\mathrm{sin}\left(\frac{{\omega }_{g}\tau }{2}\right)\) can be written as:
In the smallsignal analysis, \(\mathrm{cos}\left(\frac{{\Delta \omega }_{g}\tau }{2}\right)\approx 1\) and \(\mathrm{sin}\left(\frac{{\Delta \omega }_{g}\tau }{2}\right)\approx \frac{{\Delta \omega }_{g}\tau }{2}\). Hence, (21) can be simplified to:
Equation (20) can then be rewritten using (22), as:
The term \({\Delta \omega }_{g}\tau \left(\Delta {\theta }^{*}\Delta \widehat{\theta }+\frac{\Delta {\widehat{\omega }}_{g}\tau }{2}\frac{{\Delta \omega }_{g}\tau }{2}\right)\) in (23) equals zero in the smallsignal analysis, and \({v}_{q}\left(t\right)\) can be simplified as:
Rearranging (24) yields:
Applying the Laplace transform to (25) yields:
Substituting the value of \(\Delta {\theta }^{*}(s)\) from (16) into (26) yields:
where \({k}_{v}=2\mathrm{sin}\left(\frac{{\omega }_{n}\tau }{2}\right)\) is the amplitude scaling factor.
The derived smallsignal model does not consider the dynamic of the phase offset error, so to enhance its accuracy, compensation for the phase offset error dynamic is calculated following the guidelines in [1], where \(\delta \approx \mathrm{sin}\left(\delta \right)\approx \frac{{{\widehat{\omega }}_{g}}^{2}{{\omega }_{n}}^{2}}{k{\omega }_{n}{\widehat{\omega }}_{g}}\). Substituting the values of \({\omega }_{g}={\omega }_{n}+\Delta {\omega }_{g}\) and \({\widehat{\omega }}_{g}= {\omega }_{n}+ \Delta {\widehat{\omega }}_{g}\), \(\delta \) can be simplified to:
According to (27) and (28) and based on Fig. 1, the smallsignal model of the proposed FFSOGIPLL is shown in Fig. 2, and the closedloop transfer function is obtained as:
The transfer function in (29) contains a dominant secondorder system and a nondominant firstorder system. The dominant roots capture the dynamic performance of the system, so the smallsignal model can be reduced to a secondorder system, as:
2.2 PI gains design
From the smallsignal model represented by the dominant secondorder system as in (30), the following characteristic equation (CE) is obtained:
\({s}^{2}+{k}_{v}\left({k}_{p}\frac{\tau }{2}{k}_{i}\right)s+{k}_{v}{k}_{i}=0\). The secondorder system can be designed using linear control theory. The most straightforward method to design the PIcontroller gains is to specify the desired damping ratio \(\zeta \) and the natural damping ω_{N} of the closedloop control system. These have a specific desired transient response and bandwidth. Hence, based on \(\zeta \) and ω_{N}, the closedloop CE is obtained as \({s}^{2}+2{\omega }_{N}\zeta s+{{\omega }_{N}}^{2}=0\), and the PIcontroller gains are designed by comparing the actual CE with the desired CE. This yields \({k}_{v}{k}_{i}={{\omega }_{N}}^{2}\) and \({k}_{v}\left({k}_{p}\frac{\tau }{2}{k}_{i}\right)=2{\omega }_{N}\zeta\), from which
If \(\tau =0.002\) s, \(\zeta =0.707\), and \({\omega }_{N}=41\pi \) rad/s, the PI gains are calculated using (31) and (32) as \({k}_{p}=\) 325.1547 and \({k}_{i}=\) 27,397. The SOGI gain factor \(k\) should be as large as possible. However, the related PLL smallsignal model reveals that a lower value for \(k\) leads to better filtering capability but at the cost of a slower dynamic response. Therefore, \(k\) should be selected to achieve an acceptable tradeoff between the disturbance rejection and response speed. To make a fair comparison with other PLLs, \(k=2\) is selected.
Figure 3 shows the actual and smallsignal model responses of the proposed PLL under a phase jump of 20° at 0.02 s, while the actual and estimated voltages are shown in Fig. 4. The results in Figs. 3 and 4 validate the accuracy of the derived smallsignal model in predicting the dynamic behavior of the proposed PLL.
The performance of the proposed FFSOGIPLL is also tested under the following case studies:
Case Study 1: A 20% voltage sag is applied at 0.1 s and recovered to 1 pu at 0.2 s. At 0.3 s, a 20° phase jump occurs, while grid DC voltage offset is imposed at 0.4 s. The grid frequency is fixed at 50 Hz. The results are shown in Fig. 5.
Case Study 2: At 0.1 s, a 3 Hz frequency variation occurs in the grid, while a grid DC voltage offset is added at 0.3 s. The results are shown in Fig. 6.
3 Performance comparisons
The modified SOGIPLL [4], the modified enhanced PLL (mEPLL) [28], and the ESOGIFLL [30] are compared with the proposed PLL. There is a coupling term between the SOGI block and SRFPLL [4, 7, 31]. Hence, the gain selection of the SOGI block \(k\) can affect the system’s stability. Therefore, for a fair comparison with the other SOGIPLLs, the gain of the SOGI block needs to be as large as possible to achieve a fast dynamic response. Thus, the gain of the SOGI block is set to 2 for all PLLs, including the proposed one.
The PIcontroller gains for the modified SOGIPLL are determined based on the symmetrical optimum method because it has a thirdorder transfer function [4, 31, 32]. In the symmetrical optimum method [33], if the crossover frequency \({\omega }_{c}\) is made equal to the natural frequency \({\omega }_{N}\), the following parameters are defined:
where \(b\) is a constant that determines the phase margin (PM) and the system stability as:
For the recommended PM of 30° < PM < 60°, \(b\) is selected to be \(1+\sqrt{2}\) by considering a damping factor \(\zeta \) of 0.707 and \(PM\) of 45°, in order to guarantee sufficient system robustness and a fair comparison with the proposed PLL. In addition, \({\omega }_{N}\) is selected as 41π rad/s for all the PLLs. Hence, based on (33) and (34), the PIcontroller gains for the modified SOGIPLL are \({k}_{p}=\) 130.129 and \({k}_{i}\)= 70,141.
The PI gains for the mEPLL and ESOGIPLL are adopted to be the same as the proposed PLL for the purpose of a fair comparison. They are \({k}_{p}=\) 325.1547 and \({k}_{i}=\) 27,397.
The following case studies are considered for the comparisons:
Case 1: A phase jump of 20° at 0.04 s, and the results are shown in Fig. 7.
Case 2: A phase jump of 20° and DC offset of 0.15 pu are added to the grid voltage at 0.04 s. The results are shown in Fig. 8.
Case 3: The grid frequency is changed from 50 to 53 Hz at 0.04 s, and the results are shown in Fig. 9.
Case 4: The grid frequency is changed from 50 to 53 Hz, and a DC offset of 0.15 pu is added to the grid voltage at 0.04 s. The results are shown in Fig. 10.
Case 5: A 0.15 pu DC offset is added to the grid voltage at 0.04 s, and the results are shown in Fig. 11.
Case 6: A 0.2 pu voltage sag and a 0.15 pu DC offset are added to the grid voltage at 0.04 s. The results are shown in Fig. 12.
Several comparative simulations are carried out using MATLAB/Simulink to test the dynamic performance under a 20\(^\circ \) phase jump and 3 Hz frequency drift with and without a DC offset. The results are shown in Figs. 7–10 and are summarized in Table 1. The settling time of the proposed PLL is faster than the other PLLs by around two grid cycles, as seen in Figs. 7–10. The settling times of the modified SOGIPLL and ESOGIPLL are about four grid cycles under the phase and frequency jump with and without a DC offset, which is twice the proposed PLL. The mEPLL converges within three grid cycles. In addition, the proposed PLL has less phase overshoot than the other PLLs, while the estimated peak frequency is almost the same for all the PLLs.
The DC offset rejection performance of the proposed PLL compared with the other PLLs is depicted in Fig. 11. The settling time of the proposed PLL is around two grid cycles,
which is slightly faster than the mEPLL and the modified SOGIPLL. The settling time for the ESOGIPLL is about three gird cycles. However, the peak frequency deviation and peak phase error of the proposed PLL are less than the other PLLs.
Under the effect of the combined voltage sag and DC offset, the proposed PLL’s settling time is around two grid cycles, which is much faster than the other PLLs. The peak phase and frequency errors are also less than the other PLLs, as shown in Fig. 12.
Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all the performance indices listed in Table 1, hence offering an improved solution for precise grid synchronization in singlephase applications.
4 Experimental results
Here, the theoretical findings of the proposed PLL are experimentally verified, with comparisons made to the mEPLL and modified SOGIPLL. The smallscale setup, which consists of a voltage source inverter (VSI) connected to an R load via an LC filter to form a virtual grid, is shown in Fig. 13.
The VSI is controlled in an openloop to mimic the occurrence of different cases, such as phase jump, frequency variation, voltage sag, and DC offset. The point of common coupling is measured using an LV25P voltage sensor, and an offset and scaling circuit is used to shape the grid voltage to make it suitable for the analogtodigital converter (ADC) module.
The experimental data are processed by an Altera DE2115 fieldprogrammable gate array (FPGA) board, and a Tektronix TDS2024B digital oscilloscope is used to observe the digitaltoanalog converter (DAC) module results. The VSI switching frequency is 10 kHz, the filter has the values of L_{f} = 0.1mH and C_{f} = 10 μF, and the nominal grid frequency is 50 Hz. For the experimental validation, the arbitrary time delay τ of the proposed PLL is set to 0.005 s. This results in the PIcontroller gains of \({k}_{p}\)= 158.134 and \({k}_{i}=\) 11,731.
The estimated phase error and frequency results under a 20° phase jump are shown in Fig. 14. The results of the 3 Hz frequency drift are shown in Fig. 15. Figure 16 shows the results under a voltage sag of 0.2 pu. Finally, the results under a DC offset of 0.15 pu are shown in Fig. 17. The results show that the proposed PLL converges faster than the other PLLs and has a better dynamic performance.
It should be noted that the harmonic test is considered indirectly for all the experimental tests. The VSI with pulse width modulation and cascaded with the LC filter is a source of harmonics; the total harmonic distortion in the sensed grid voltage is 11.69%.
The experimental results verified the simulations. This validates the applicability of the proposed PLL as an improved synchronization technique for singlephase applications.
5 Conclusion
In this paper, a new DC offset rejection method using an ADSC operator has been proposed for gridconnected converters in singlephase applications that is not limited to a specific time delay. The proposed PLL adopts a fixedfrequency SOGI to decrease the implementation complexity, enhance relative stability, and simplify the control design. Although other PLLs rely on a specified delay value to reject DC offset, the proposed method is not restricted to a specific time delay. Moreover, unlike other PLLs that rely on a SOGI, the proposed PLL can be accurately represented by a dominant secondorder system, which simplifies the controller design. The statistical results of the numerical simulations under different cases, such as phase jump, frequency variation, voltage sag, and DC offset, show that the proposed PLL has the fastest transient response and better dynamic performance than other PLLs on almost all performance indices. The performance of the proposed PLL is experimentally validated and compared with the analytical results. They show a better dynamic performance than other PLLs. Therefore, the proposed PLL offers an improved solution for precise grid synchronization.
Availability of data and materials
All data generated or analyzed during this study are included in the published article.
Abbreviations
 ADSC:

Arbitrarily Delayed Signal Cancellation
 ADC:

AnalogtoDigital Converter
 CE:

Characteristic Equation
 CGI:

Cascaded Generalized Integrator
 DAC:

digitaltoanalogeconverter
 ESOGIPLL:

Enhanced structure SOGIPLL
 FFSOGIPLL:

FrequencyFixed SOGIbased PLL
 FLL:

FrequencyLocked Loop
 FPGA:

FieldProgrammable Gate Array
 mEPLL:

Modified Enhanced PLL
 MSTOGI:

Mixed Second and ThirdOrder Generalized Integrator
 OSG:

Orthogonal Signal Generation
 PCC:

The Point of Common Coupling
 PI:

ProportionalIntegral
 PM:

The Phase Margin
 PLL:

PhaseLocked Loop
 SOGI:

SecondOrder Generalized Integrator
 SRFPLL:

Synchronous Reference Framebased PLL
 THD:

Total Harmonic Distortion
 TOGI:

ThirdOrder Generalized Integrator
 A, B, \( \varphi_{1}\), \(\varphi_{2}\) and \(\omega_{d}\) :

Variables function of \(\omega_{g}\), \(\omega_{n }\), and \(k\).
 \(b\) :

The constant that determines the phase margin
 \(D\left( t \right)\) & \(Q\left( t \right)\) :

Terms decaying to zero at time constant equal \(\tau_{p}\)
 \(\delta\) :

The phase offset error
 \(\Delta \omega_{g}\) :

The deviation of the grid frequency from its nominal value
 \(\Delta \hat{\omega }_{g}\) :

The deviation in estimated grid frequency
 \(\Delta \theta^{*}\) :

The deviation in the estimated value of the phase error compensator
 \(\Delta \widehat{\theta }\) :

The deviation in the estimated phase
 \(\Delta \theta \) :

The deviation in the grid voltage phase
 \(\Delta {v}_{\alpha \beta }\left(t\right)\) :

The signals after the ADSC operator
 k :

The SOGI block’s gain factor
 \({k}_{v}\) :

The amplitude scaling factor
 \({k}_{p}\) :

The proportional gain of the PIcontroller
 \({k}_{i}\) :

The integral gain of the PIcontroller
 τ :

The delay length of the ADSC
 \({\tau }_{p}\) :

The time constant of FFSOGIPLL
 \(\theta \) :

Grid voltage phase
 \(\widehat{\theta }\) :

The estimated phase
 \({\theta }^{*}\) :

The net phase angle difference at the grid side
 V :

The grid amplitude
 \({v}_{\alpha }\left(t\right)\) &\({v}_{\beta }\left(t\right)\) :

The timedomain αβ signals
 v _{ i } :

The grid voltage
 ω _{ n } :

The nominal grid frequency
 \({\omega }_{g}\) :

The actual grid frequency
 \({\widehat{\omega }}_{g}\) :

The estimated grid frequency
 ω_{N} :

The natural frequency
 \({\omega }_{c}\) :

The crossover frequency
 \(\zeta \) :

The desired damping ratio
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This work was supported by the Deanship of Research at Jordan University of Science and Technology (Grant number: 20210333).
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Issam A. Smadi proposed the research idea formulations and built the experimental setup. All authors participated in formulating the control design and in implementing it. Bayan H. Bany Fawaz was in charge of running different simulations and writing the first draft of the paper. Issam A. Smadi updated the literature review and improved the quality of the presentation. All authors participated in verifying the results and providing answers to all comments from reviewers. All authors read and approved the final manuscript.
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Smadi, I.A., Bany Fawaz, B.H. DC offset rejection in a frequencyfixed secondorder generalized integratorbased phaselocked loop for singlephase gridconnected applications. Prot Control Mod Power Syst 7, 1 (2022). https://doi.org/10.1186/s4160102100223w
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DOI: https://doi.org/10.1186/s4160102100223w