Fig. 7From: DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applicationsPerformance comparison between the proposed PLL, ESOGI-PLL, modified SOGI-PLL, and mEPLL under Case 1 (a phase jump of 20° at 0.04 s). a Estimated phase error and b estimated grid frequencyBack to article page