Fig. 8
![Fig. 8](http://media.springernature.com/full/springer-static/image/art%3A10.1186%2Fs41601-021-00223-w/MediaObjects/41601_2021_223_Fig8_HTML.png)
Performance comparison between the proposed PLL, ESOGI-PLL, modified SOGI-PLL, and mEPLL under Case 2 (a phase jump of 20° and a DC offset of 0.15 pu added to the grid voltage at 0.04 s). a Estimated phase error and b estimated grid frequency