Fig. 11
![Fig. 11](http://media.springernature.com/full/springer-static/image/art%3A10.1186%2Fs41601-021-00223-w/MediaObjects/41601_2021_223_Fig11_HTML.png)
Performance comparison between the proposed PLL, ESOGI-PLL, modified SOGI-PLL, and mEPLL under Case 5 (a 0.15 pu DC offset added to the grid voltage at 0.04Â s). a Estimated phase error and b estimated grid frequency
Performance comparison between the proposed PLL, ESOGI-PLL, modified SOGI-PLL, and mEPLL under Case 5 (a 0.15 pu DC offset added to the grid voltage at 0.04Â s). a Estimated phase error and b estimated grid frequency