Fig. 11From: DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applicationsPerformance comparison between the proposed PLL, ESOGI-PLL, modified SOGI-PLL, and mEPLL under Case 5 (a 0.15 pu DC offset added to the grid voltage at 0.04Â s). a Estimated phase error and b estimated grid frequencyBack to article page