Fig. 17From: DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applicationsExperimental results under a 0.15 pu DC offset. CH1, CH2, and CH3 show the responses of the proposed PLL, mEPLL, and modified SOGI-PLL, respectively. a Estimated phase error and b estimated grid frequencyBack to article page