DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

Protection and Control of Modern Power Systems

Table 1 Summarized results for the different PLLs and the proposed PLL

Case study	Proposed FFSOGI-PLL	ESOGI-PLL	Modified SOGI-PLL	mEPLL
20° phase jump
2% phase settling time (ms)	41.60	92.90	86.30	64.50
Phase overshoot (%)	40.3835	49.81	54.01	49.84
Peak frequency (Hz)	52.81	53.33	52.74	53.26
20° phase jump and 0.15 pu DC offset
2% phase settling time (ms)	42.40	95.30	89.10	71.30
Phase overshoot (%)	45.89	50.41	59.78	51.77
Peak frequency (Hz)	53.40	53.80	53.24	54.31
3 Hz frequency jump
2% frequency settling time (ms)	47.80	79.40	74.00	64.7
Frequency overshoot (%)	0.26	1.10	0.44	0.65
Peak phase error (°)	6.65	7.85	9.71	6.31
Peak frequency (Hz)	53.10	53.58	53.23	53.34
3 Hz frequency jump and 0.15 pu DC offset
2% frequency settling time (ms)	48.20	78.30	69.90	71.10
Frequency overshoot (%)	0.69	2.39	0.72	2.05
Peak phase error (°)	14.91	16.55	19.67	18.23
Peak frequency (Hz)	53.37	54.27	53.38	54.09
0.15 pu DC offset only
2% phase settling time (ms)	43.60	74.70	50.10	47.50
Absolute peak phase error (°)	8.43	8.84	9.87	11.83
Peak frequency deviation (Hz)	1.09	1.29	1.12	1.81
Amplitude reduced by 0.2 pu and 0.15 pu DC offset
2% phase settling time (ms)	40.30	83.40	66.60	82.50
Peak phase error (°)	5.19	7.23	15.68	21.99
Peak frequency deviation (Hz)	0.79	1.22	1.82	3.70