Fig. 10From: DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applicationsPerformance comparison between the proposed PLL, ESOGI-PLL, modified SOGI-PLL, and mEPLL under Case 4 (a frequency jump of 3Â Hz and a DC offset of 0.15 pu added to the grid voltage at 0.04Â s). a Estimated phase error and b estimated grid frequencyBack to article page