A novel hybrid cybersecurity scheme against false data injection attacks in automated power systems

Protection and Control of Modern Power Systems

Table 5 Computational delays of cybersecurity mechanism for SV packets

Scheme	Computational time in ms	Platform utilized	Lower than Inter-arrival time
M. Rodríguez et al. [13]	0.006	Zynq 7020 FPGA	✓
M. El Hariri et al. [18]	0.29	ODROID C2 microcontroller	×
T. S. Ustun et al. [19]	0.049	Intel Core i7 @ 2.80 GHz 32 GB RAM	✓
This work	0.013	Intel Core i7 @ 1.80 GHz 16 GB RAM	✓