Fig. 13From: Transient synchronous stability analysis and enhancement control strategy of a PLL-based VSC system during asymmetric grid faultsSimulation results under different detection delays. a Positive sequence d-axis voltage. b Positive sequence d-axis current. c Positive sequence q-axis current. d Positive sequence PLL output frequency. e Negative sequence d-axis voltage. f Negative sequence d-axis current. g Negative sequence q-axis current. h Negative sequence PLL output frequencyBack to article page