DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

Fast and accurate monitoring of the phase, amplitude, and frequency of the grid voltage is essential for single-phase grid-connected converters. The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters. In this paper, a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation (ADSC) in a second-order generalized integrator (SOGI) phase-locked loop (PLL). A frequency-fixed SOGI-based PLL (FFSOGI-PLL) is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs. A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral (PI) controller gains. The effects of frequency variation and ADSC on the proposed PLL are considered, and correction methods are adopted to accurately estimate grid information. The simulation results are presented, along with comparisons to other single-phase PLLs in terms of settling time, peak frequency, and phase error to validate the proposed PLL. The dynamic performance of the proposed PLL is also experimentally validated. Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices, offering an improved solution for precise grid synchronization in single-phase applications.


Introduction
Renewable energy sources are integrated into the grid using grid-synchronized voltage source converters. A precise grid synchronization algorithm influences the power, quality, and reliability of the grid. However, many issues must be overcome to avoid synchronizationrelated problems. The presence of DC offset in the grid voltage is considered a significant problem, affecting the operation of grid-connected converters and power quality [1][2][3].
Voltage and current sensors, signal conditioning circuits, quantification errors in the analog-to-digital-conversion process, the mismatch of power semiconductor parameters, and current circulating between inverters are considered the major causes of DC offset in grid voltage [2][3][4][5][6][7][8][9][10]. The presence of DC offset not only deteriorates the performance of grid synchronization units but also affects the closed-loop stability of grid-connected converters because of oscillations in the estimated grid frequency, phase, and voltage amplitude [2][3][4].
Much published research is related to orthogonal signal generation (OSG) methods used with single-phase phase-locked loops (PLLs) to create fictitious quadrature signals. Among the many reported OSG-based PLLs, the second-order generalized integrator (SOGI) PLL has become the most popular for single-phase applications because of its low computation burden, straightforward implementation, and high filtering capability for loworder harmonics [1-4, 11, 12]. The SOGI-PLL uses an OSG block to generate orthogonal signals from the single-phase grid voltage [2]; to implement the synchronization function, these are fed to the synchronous reference frame-based PLL (SRF-PLL) [13]. To ensure the accurate detection of frequency, voltage amplitude, and phase angle, the estimated SRF-PLL frequency is fed back to the SOGI block, making the SOGI-PLL frequency adaptive. However, this feedback increases the complexity of the design, and the design of loop filter gains becomes difficult [14].
Several SOGI-based PLLs have been reviewed in terms of their ability to remove the effect of DC offset from the grid synchronization process [4,7]. These methods include the cascaded SOGI-PLL, modified SOGI-PLL, αβDSC 2 with SOGI-PLL, in-loop dq-frame DSC, complex-coefficient filter, notch filter, and moving average filter-based SOGI-PLL. The αβDSC 2 , SOGI-PLL, and modified SOGI-PLL have the shortest settling time when removing DC offset compared with the other SOGI-PLLs. However, all these PLLs have a slow dynamic response, and the closed-loop transfer function is of the third-order, which complicates controller design.
Reference [6] proposes a cascaded generalized integrator (CGI)-based PLL consisting of two cascaded SOGI blocks. To reject DC offset, an SRF-PLL adopting a frequency-fixed procedure is used to ensure stability and simple implementation. The two parameters that must be carefully adjusted to avoid affecting the PLL's transient performance and harmonic filtering capability are designed to minimize the overall settling time of the PLL. However, because CGI-PLL suffers from attenuation to low-order harmonics, the SRF-PLL bandwidth must also be carefully selected to avoid unbalancing the quadrature signals. Also, using two SOGI blocks in a cascade to remove DC offset increases the system's complexity. In [15], a dual SOGI and moving average filter in-loop with the SRF-PLL are combined to form a hybrid filter-based PLL. This method blocks the fundamental frequency negative sequence component, DC offset, and dominant harmonic components and has a relatively fast transient response. However, the transient response performance depends on the window length of the hybrid filter.
A mixed second-and third-order generalized integrator (MSTOGI)-based PLL is presented in [16,17]; it contains an extra branch to the SOGI block to eliminate DC offset and high-frequency harmonics from input signals. The MSTOGI gain affects the filtering capability, dynamic performance, and bandwidth of the SRF-PLL. Therefore, the MSTOGI-PLL controller gain has to match the MSTOGI gain to maintain stability and optimize the settling time. The dynamic performance of the MSTOGI-PLL is proportional to its bandwidth, so a high bandwidth must be chosen to achieve a faster transient response. However, a higher bandwidth weakens the ability to suppress low-frequency harmonics in the grid voltage. The system stability and pole trajectory aspects of generalized SOGI and TOGI-based PLLs have been investigated in [18]. Although a TOGI has advantages over a SOGI under harmonically distorted grid conditions, it is more complicated than a SOGI.
In [19], a frequency-locked loop (FLL) control method is used to eliminate DC offset, in which the FLL controller is combined with a modified SOGI block to estimate and obliterate DC offset from grid voltage. In general, since frequency adaptation is highly nonlinear, the linear control analysis technique cannot be directly applied, and thus it increases the design complexity. Also, the dynamic response of the SOGI-FLL depends on the adequate selection of the FLL and SOGI gains. The complexity and computational burden of frequency-fixed SOGI-based PLL (FFSOGI-PLL) is notably reduced compared with the classical SOGI-PLL. This allows for higher bandwidth, better stability margin, and faster dynamic response. However, with grid frequency variation, FFSOGI-PLL suffers from double-frequency harmonics related to bandwidth selection [20].
The SOGI-FLL with fixed frequency proposed in [21] incorporates a low pass filter with notch characteristics and a linearized phase error compensation to mitigate the double-frequency oscillation in the estimated grid information. Although this FLL has straightforward parameter tuning and selective harmonic rejection capability based on a linearized phase-loop transfer function, it has limited DC offset rejection capability. In [22], a solution is proposed for the double-frequency term and offset error in the frequency-fixed SOGI using a conformal mapping-based fractional-order approach. The PLL shows good dynamic performance during different disturbances, including DC offset, by adjusting the fractional-order gain according to grid frequency variations. However, the use of fractional-order calculus increases system complexity and computational burden. A discrete-time non-adaptive SOGI-FLL based on a gradient descent algorithm is presented in [23]. Although its dynamic performance is smooth and fast, the method cannot completely reject DC offset.
A type 3 modified SOGI-PLL is presented in [24], addressing the slow dynamic response, instability under voltage sag, and poor damping under other abnormal grid conditions by enhancing the gain and phase margins using gain and phase-lead compensators. This PLL  [25] to add a DC offset rejection capability to the PLL using the notch filter. A trade-off between the filtering capability and dynamic performance is recommended in assigning the SOGI-PLL parameters. In addition, the design of the loop filter gains becomes difficult since the overall transfer function is of a high order. An enhanced structure SOGI-PLL (ESOGI-PLL) is proposed in [26]. This has a simple design and adequate performance when exposed to high DC offset values. However, the gain of the ESOGI-PLL should be selected carefully so that it does not deteriorate the transient response and harmonic attenuation capability. Two types of PLLs combining an open-loop frequencyestimator and SOGI block are introduced in [27] using different normalization schemes to remove the dependency of the frequency estimator on grid frequency or phase angle information. The DC offset is canceled using an extra integrator added to the SOGI block to provide accurate grid information estimation with four grid cycles convergence speed. The computation burden of this PLL is reduced using a third-order polynomial approximation to implement the arctangent function, but this comes at the cost of accuracy. Reference [28] discusses many PLLs and FLLs, though most PLLs are either for three-phase systems or based on open-loop PLL structures. The open-loop PLL is beyond the scope of this paper, while because of a lack of signal orthogonality, the design of a single-phase PLL is more challenging than that for three-phase systems.
This paper presents a new method for removing the DC offset effect from a grid synchronization unit using arbitrarily delayed signal cancelation (ADSC) in a SOGI-PLL. A frequency-fixed procedure is adopted to ensure stability and reduced complexity compared with other SOGI-based PLLs. Unlike other PLLs that rely on a SOGI, the proposed PLL can be accurately represented by a dominant second-order system, making the loop filter design process straightforward. Moreover, the DC offset rejection capability of the proposed method is not restricted to a specific time delay. This gives the proposed PLL more flexibility than other related PLLs. A smallsignal model of the proposed PLL is derived for the systematic design of proportional-integral (PI) controller gains. The effects of frequency variations and ADSC on the proposed PLL are considered, and phase and voltage amplitude correction methods are adopted to accurately estimate grid information.
The rest of the paper is organized as follows: Sect. 2 introduces the proposed method, including the required mathematical justifications, the small-signal model, and the PI-controller gain design. Numerical simulations are presented in Sect. 3 to verify and justify the derived small-signal model. Experimental results compared with other related PLLs under different case studies are discussed in Sect. 4, and Sect. 5 concludes the paper. Figure 1 presents the proposed FFSOGI-PLL, which adopts a fixed-frequency concept to reduce implementation complexity, enhance relative stability, and simplify the control design following the recommendations in [14]. As shown in Fig. 1, an ADSC operator is used to cancel the DC offset from the orthogonal signals, v i is the grid voltage, ω n is the nominal grid frequency, and ω g and θ are the estimated grid frequency and phase angle, respectively. τ is the delay length of the ADSC, and k is the SOGI block gain factor. As shown in Fig. 1, the estimated frequency from the SRF-PLL is fed back to the SOGI block to make it frequency adaptive.

Proposed method
The transfer functions of the fixed-frequency SOGI block, as shown in Fig. 1, are: Fig. 1 The proposed FFSOGI-PLL with DC offset rejection capability. The SOGI is used to construct the orthogonality. Arbitrarily delayed signal cancelation is used to remove the DC offset from the orthogonal signals Assuming a grid voltage of v i (t) = V sin ω g t , where V is the voltage amplitude and it is assumed to be 1 pu for simplicity, the Laplace transform for the grid voltage is obtained as: The output voltage in the s-domain of the SOGI, assuming fixed frequency for a given input voltage, is written as: Simplifying the partial fraction expansion, the time domain αβ-signals v α (t) and v β (t) are obtained as: and ω d are functions of ω g , ω n , and k. From (6) and (7), it can be seen that v α (t) and v β (t) have different amplitudes if ω g = ω n . As ω n 2 − ω 2 g ≪ kω n ω g , (6) and (7) can be simplified as: From (8) and (9), the v α (t) amplitude is equal to 1, while the v β (t) amplitude is scaled by ω n /ω g . The signals after the ADSC operator are given as: Substituting (8) and (9) into (10) and (11) yields: where The terms D(t) and Q(t) decay to zero with the time constant τ p = 2/kω n . Therefore, (12) and (13) are simplified as: where θ = ω g t . Using a fixed frequency in the SOGI block, v α (t) is the orthogonal signal to v β (t) ω g /ω g in the frequency-locked state ( ω g = ω g ). Hence, any variation in the grid frequency will result in a small phase difference δ between the actual phase angle θ and that of v α (t).
If θ * is the net phase angle difference at the grid side and θ * = θ − δ , the transfer function of the SOGI block can be written as: Equations (14) and (15) can be expressed using θ * as: Using ADSC to reject the DC offset will cause a phase error, so a phase correction of θ 0 = − ω g τ 2 is needed [9,29]. The v q (t) signal with the phase correction can be obtained as: which can be simplified to:

PLL small-signal model
In this section, a small-signal model for the proposed PLL is derived. The term sin ω g τ 2 can be written as: In the small-signal analysis, cos Hence, (21) can be simplified to: Equation (20) can then be rewritten using (22), as: The term �ω g τ �θ * − � θ + in (23) equals zero in the small-signal analysis, and v q (t) can be simplified as: Rearranging (24) yields: sin Applying the Laplace transform to (25) yields: Substituting the value of �θ * (s) from (16) into (26)  yields: where k v = 2sin ω n τ 2 is the amplitude scaling factor. The derived small-signal model does not consider the dynamic of the phase offset error, so to enhance its accuracy, compensation for the phase offset error dynamic is calculated following the guidelines in [1], where Substituting the values of ω g = ω n + �ω g and ω g = ω n + � ω g , δ can be simplified to: According to (27) and (28) and based on Fig. 1, the small-signal model of the proposed FFSOGI-PLL is shown in Fig. 2, and the closed-loop transfer function is obtained as: The transfer function in (29) contains a dominant second-order system and a nondominant first-order system. The dominant roots capture the dynamic performance of the system, so the small-signal model can be reduced to a second-order system, as:

PI gains design
From the small-signal model represented by the dominant second-order system as in (30), the following characteristic equation (CE) is obtained: The second-order system can be designed using linear control theory. The most straightforward method to design the PI-controller gains is to specify the desired damping ratio ζ and the natural damping ω N of the closed-loop control system. These have a specific desired transient response and bandwidth. Hence, based on ζ and ω N , the closedloop CE is obtained as s 2 + 2ω N ζ s + ω N 2 = 0 , and the PI-controller gains are designed by comparing the actual CE with the desired CE. This yields k v k i = ω N 2 and k v k p − τ 2 k i = 2ω N ζ , from which If τ = 0.002 s, ζ = 0.707 , and ω N = 41π rad/s, the PI gains are calculated using (31) and (32) as k p = 325.1547 and k i = 27,397. The SOGI gain factor k should be as large as possible. However, the related PLL small-signal model reveals that a lower value for k leads to better filtering capability but at the cost of a slower dynamic response. Therefore, k should be selected to achieve an acceptable trade-off between the disturbance rejection and response speed. To make a fair comparison with other PLLs, k = 2 is selected.

Performance comparisons
The modified SOGI-PLL [4], the modified enhanced PLL (mEPLL) [28], and the ESOGI-FLL [30] are compared with the proposed PLL. There is a coupling term between the SOGI block and SRF-PLL [4,7,31]. Hence, Fig. 2 The small-signal model of the proposed FFSOGI-PLL, where τ is the arbitrary time delay and τ p = 2/kω n is the time constant of the SOGI block  the gain selection of the SOGI block k can affect the system's stability. Therefore, for a fair comparison with the other SOGI-PLLs, the gain of the SOGI block needs to be as large as possible to achieve a fast dynamic response. Thus, the gain of the SOGI block is set to 2 for all PLLs, including the proposed one.
The PI-controller gains for the modified SOGI-PLL are determined based on the symmetrical optimum method because it has a third-order transfer function [4,31,32]. In the symmetrical optimum method [33], if the crossover frequency ω c is made equal to the natural frequency ω N , the following parameters are defined: where b is a constant that determines the phase margin (PM) and the system stability as: For the recommended PM of 30° < PM < 60°, b is selected to be 1 + √ 2 by considering a damping factor ζ of 0.707 and PM of 45°, in order to guarantee sufficient system robustness and a fair comparison with the proposed PLL. In addition, ω N is selected as 41π rad/s for all the PLLs. Hence, based on (33) and (34), the PI-controller gains for the modified SOGI-PLL are k p = 130.129 and k i = 70,141.
The PI gains for the mEPLL and ESOGI-PLL are adopted to be the same as the proposed PLL for the purpose of a fair comparison. They are k p = 325.1547 and k i = 27,397.
The following case studies are considered for the comparisons: Case 1: A phase jump of 20° at 0.04 s, and the results are shown in Fig. 7.
Case 2: A phase jump of 20° and DC offset of 0.15 pu are added to the grid voltage at 0.04 s. The results are shown in Fig. 8.

Case 3:
The grid frequency is changed from 50 to 53 Hz at 0.04 s, and the results are shown in Fig. 9.    by around two grid cycles, as seen in Figs. 7-10. The settling times of the modified SOGI-PLL and ESOGI-PLL are about four grid cycles under the phase and frequency jump with and without a DC offset, which is twice the proposed PLL. The mEPLL converges within three grid cycles. In addition, the proposed PLL has less phase overshoot than the other PLLs, while the estimated peak frequency is almost the same for all the PLLs. The DC offset rejection performance of the proposed PLL compared with the other PLLs is depicted in Fig. 11. The settling time of the proposed PLL is around two grid cycles, which is slightly faster than the mEPLL and the modified SOGI-PLL. The settling time for the ESOGI-PLL is about three gird cycles. However, the peak frequency deviation and peak phase error of the proposed PLL are less than the other PLLs.
Under the effect of the combined voltage sag and DC offset, the proposed PLL's settling time is around two grid cycles, which is much faster than the other PLLs. The peak phase and frequency errors are also less than the other PLLs, as shown in Fig. 12.
Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all the performance indices listed in Table 1, hence offering an improved solution for precise grid synchronization in single-phase applications.

Experimental results
Here, the theoretical findings of the proposed PLL are experimentally verified, with comparisons made to the mEPLL and modified SOGI-PLL. The small-scale set-up, which consists of a voltage source inverter (VSI) connected to an R load via an LC filter to form a virtual grid, is shown in Fig. 13.
The VSI is controlled in an open-loop to mimic the occurrence of different cases, such as phase jump, frequency variation, voltage sag, and DC offset. The point of common coupling is measured using an LV25-P voltage sensor, and an offset and scaling circuit is used to shape the grid voltage to make it suitable for the analog-to-digital converter (ADC) module.
The experimental data are processed by an Altera DE2-115 field-programmable gate array (FPGA) board, and a Tektronix TDS2024B digital oscilloscope is used to observe the digital-to-analog converter (DAC) module results. The VSI switching frequency is 10 kHz, the filter has the values of L f = 0.1mH and C f = 10 μF, and the nominal grid frequency is 50 Hz. For the experimental validation, the arbitrary time delay τ of the proposed PLL is set  Figure 16 shows the results under a voltage sag of 0.2 pu. Finally, the results under a DC offset of 0.15 pu are shown in Fig. 17. The results show that the proposed PLL converges faster than the other PLLs and has a better dynamic performance.
It should be noted that the harmonic test is considered indirectly for all the experimental tests. The VSI with pulse width modulation and cascaded with the LC filter is a source of harmonics; the total harmonic distortion in the sensed grid voltage is 11.69%.
The experimental results verified the simulations. This validates the applicability of the proposed PLL as an improved synchronization technique for single-phase applications.  The natural frequency; ω c : The crossover frequency; ζ: The desired damping ratio.

Availability of data and materials
All data generated or analyzed during this study are included in the published article.