A cumulative standard deviation sum based method for high resistance fault identification and classification in power transmission lines

Abstract

High resistance fault poses an enormous challenge to the existing algorithms of fault detection and fault classification. In this paper, the standard deviation and accumulation method are employed to perform the fault detection and classification. It is primarily built in two stages. Firstly, the standard deviations for the measured current’s signals of the local and remote terminals is computed to extract the fault feature. Secondly, the cumulative approach is used to enlarge the fault feature to perform the high resistance fault. The proposed scheme is known as Standard Deviation Index (SDI), and it is obtained for the three phases and zero sequence. The proposed algorithm has been tested through different fault circumstances such as multiple faults locations, fault resistances, and fault inception time. Moreover, far-end faults with high-resistance, faults happened nearby the terminal, faults considering variable loading angle, sudden load change, different sampling frequency, bad signaling and a fault occurred in the presence of series compensation are also discussed. The results show that the proposed scheme performed remarkably well regarding the fault with resistance up to 1.5kΩ and can be detected within a millisecond after the fault inception. Additionally, the computational simplicity that characterizes the processes makes it more efficient and suitable for domain applications.

1 Introduction

The rapid growth of electric power systems over the past few decades has resulted in significant increase in the number of transmission lines. This development exposes the system to an unexpected fault which results in short to long-term power outages. Once a fault occurs on such lines, the relay must quickly detect and isolate the faulty lines, and then the fault classification should carried out [1].

Many researchers reported different techniques for fault detection and classification. Among these various methods, wavelet-based techniques. It is characterized by its ability to track the transient phenomena that associates the faults [2]. Artificial intelligence techniques such as Artificial Neural Network (ANN), Fuzzy, and Artificial Neural Network Fuzzy inference system (ANFIS), have an extensive usage in faults detection and classification process in power transmission line [3,4,5,6,7]. Hybrid techniques were coming out to overcome the drawbacks of one approach during its application. The Basic hybrid techniques are classified into four types Neuro-fuzzy technique, Wavelet and ANN technique, Wavelet and fuzzy-logic technique, and Wavelet-neuro-fuzzy technique [8]. The particle swarm optimization (PSO) combined with ANN is applied for the fault classification in [9]. Fuzzy logic is used for fault phase identification and classification in [5]. Support vector machines (SVM) used for fault classification in reference [10]. The main idea of SVM classifiers is to find an optimal hyperplane that maximizes the margin between two groups of examples. By using non-linear kernel functions which classify the groups into higher dimensional spaces, at this moment, it could be easy to obtain non-linear SVM classifiers. In the scheme [11] the dynamic features were extracted by stationary wavelet transform and then fed to the support vector machine for performing the arcing faults detection in distribution system. Discrete Wavelet Transform (DWT) and Karen Bell Transformation (KBT) has been used for the fault analysis process in [12]. Functional analysis and computational intelligence are also proposed for detection and classification of faults in power transmission lines as in [13]. An adaptive cumulative-sum-based approach for detecting and classifying various faults in power transmission line has been introduced in [14], and it has attained a better dependability regarded to the fault detection and classification process. However, one of the factors that could affect its distinctiveness is taking the current samples of each phase and then dividing into positive half cycles and negative half cycles. The scheme in [15] proposed a technique for fault classification using the magnitude of differential power (MODP). The scheme relies on the results of comparing the fault phase threshold that is obtained from DT (decision tree) with MODPs of the three phases to identify the faulted phase. DT training process is performed offline which made the computational burden does not impose any delay on the operation of the protective relay. However, it requires the symmetrical transfer matrix of voltages and currents of the remote terminal for accomplishment the fault detection process. The scheme also requires a pre-established decision logic [16]. The scheme in [17] presented a reliable method of high resistance fault detection meant for current differential protections of two-terminal transmission lines up to 1 kΩ. This scheme relies on the calculation of line differential admittance in pre-fault and in faulty conditions. The scheme in [18] discusses the high resistance fault up to 200 Ω. However, both schemes require deep knowledge of the transmission line sequence components (positive, negative, and zero) of voltages and currents that measured at buses which considered an extra computation cost. The scheme in [19] utilises the relative phase angle relationship between the negative and zero sequence currents and the fault impedance to identify the fault phase. It is discussed single to ground fault and double line to ground fault up to resistance 800 Ω.

However, most schemes which use sequence component of the voltage and current signals are highly affected by the inclusion of FACT devices [20]. Wavelet transform requires a good knowledge of mother wavelet to decide the properties of the filter banks. Additionally, it requires an appropriate decomposition levels before creating the feature [21]. AI techniques require an appropriate training process, and these may increase the challenges practically especially for the huge systems with wide variation in faults [14, 22,23,24,25,26]. Conventional distance protections are facing some challenges to deal with far-end high resistance faults. The apparent impedance that seen by the relay may go out of the zone and causing under-reach operation due to the presence of fault resistance [25, 27].

Towards this end, the present study proposes a simple technique further sensitive to the high resistance faults in power transmission lines. The proposed scheme can be integrated with conventional distance protection to assist in the discrimination of high resistance faults that occur at the far-end. The process of faults detection and classification of the proposed scheme is performed by taking the current signals measured at both terminals and then dividing into small samples based on the sampling rate of signals. Then, the standard deviation is obtained for an i^th current sample. After that, accumulation method is employed to amplify the fault features of the faulted phases. The output is named as standard deviation indices (SDI). It is found that the SDI values during the fault condition are much higher than SDI during the health period. Further, the threshold value has been determined on the basis of this observation. Then, the fault detection is performed when the SDI of the three phases are higher than zero. This feature can use for the classification processes, where SDI of the faulted phases are much higher than zero while the health phases are zero.

2 Method

This item is discussed in two parts as follows.

2.1 The proposed scheme basic theory

The standard deviation the most common tool for measuring the variability and the spread out of the data set. It is used for quantifying the existing relationship between the mean and the remnant of the data. Suppose the data points are close to the mean, indicating that the responses are relatively uniform, then the standard deviation will be small. Conversely, if the data points are far from the mean, showing that the responses will be a wide variance, then the standard deviation will be considerable. If all the data values are equal, then the standard deviation will be zero. The following formula can obtain the standard deviation.

$$ \sigma =\sqrt{\frac{1}{n}\sum \limits_{i=1}^n{\left({x}_i-\overline{x}\right)}^2} $$

(1)

Where σ denotes standard deviation; x_i denotes each value of dataset [28]. It is representing the three-phase current signals and zero sequence current (I_A, I_B, I_C, and I₀) which obtained according to the formula described as follow:

$$ \left\{\begin{array}{c}{I}_A={I}_{\mathrm{sA}}+{I}_{rA}\\ {}{I}_B={I}_{\mathrm{sB}}+{I}_{rB}\\ {}{I}_C={I}_{\mathrm{sC}}+{I}_{rC}\\ {}{I}_0=\frac{I_A+{I}_B+{I}_C}{3}\end{array}\right. $$

(2)

The symposium s denotes the sending end, r denotes the receiving end, and A, B, C indicate the three phases. $\overline{x}$denotes the arithmetic mean of the data and n denotes the total number of the data.

2.2 The proposed scheme methodology

It is well known that the sinusoidal current waveform repeats each cycle, and therefore during the normal operation no difference in the standard deviation of the latest sample of the current signal compared to the samples of the previous cycle. However, when an abrupt change happens in the current signals due to fault, there is a significant difference between the standard deviation of the samples at fault instant and the standard deviation of samples of pre-fault condition. Therefore, the sum of standard deviation values for i^th samples over one cycle can be expressed as follows:

$$ \sigma s(k)=\left|\sum \limits_{j=k-N+1}^k\sigma (j)\right| $$

(3)

N represents the number of samples in the cycle; j, k represents the sampling instant. It is noted that σsduring the fault period is much higher than σs during the health period. Thus, the cumulative sum equation is helpful to amplify the difference between σs during the health and fault condition. The output is named standard deviation indices and it would take its value based on the following equation.

$$ SDI(i)=\max \left[0,\left( SDI\left(i-1\right)+\sigma s(i)- thrs\right)\right] $$

(4)

Where i = 2, …, k, SDI resents the standard deviation indices, SDI(i-1) represents the starting point, where SDI (1) is zero. It is observed that during the safe power operation the output of eq. (3) is less than the specific value, and it is exceeding this value during the fault period. This particular value was taken as a threshold (thrs) which chosen 10% more thanσs(i)during the safe operation. The threshold of each phase is obtained individually, where thrs_A, thrs_B, thrs_C, and thrs₀ represent the threshold for phase A, phase B, phase C, and zero sequence current. The threshold of zero sequence current was taken two times the standard deviation of zero sequence current σs₀. During the fault, the amplitude of zero sequence current is much higher than that in the health condition, and then thrs₀ was taken two-time σs₀. The fault detection classification process is shown in Fig. 1, and it can be concluded into steps as follows:

• Step 1. Calculate the current signals I_A, I_B, I_C, and I₀ based on eq. (2).

• Step 2. Calculate the standard deviation indices (SDI) using eq. (4) for phase A, phase B, phase C, and zero sequence current separately (SDI_A, SDI_B, SDI_C, and SDI₀).

• Step 3. Perform the fault detection and classification process which can be as follows:

Fig. 1

Flow chart of the proposed scheme

If SDI_A, SDI_B, SDI_C, = zero; indicating that, the system is running in the safe operating condition. Otherwise, the system was subjected to the fault condition, and then perform the fault classification process, where:

• SDI of the faulted phases > zero

• SDI of the healthy phases = zero

• In the case of ground faults, SDI₀ > zero

• In case of non-ground fault, SDI₀ = zero

SDI₀ used for distinguishing the phase fault (line to line and three-line fault) from the ground fault (single line, double line and triple line to ground fault).

3 Results and Discussion

Figure 2 shows the schematic diagram of the WSCC system (IEEE 9 bus system), established in PSCAD/EMTDC by Manitoba HVDC Research Center. It was employed for obtaining the current signals that will be used to perform the proposed scheme tests. The model consists three synchronous machines with built-in voltage and speed regulators, three two-winding transformers, six constant parameters lines and three loads. More details are provided in the Appendix. The voltage and current signals are sampled at a rate of 4 kHz, about 80 samples per cycle. The current measurements are obtained from CTs sets with burden 5 Ω and turn ratio 1000/5 installed in the sending end and receiving end respectively. Then the current signals were exported to MATLAB environment and given as input to the algorithm to develop the fault detection and classification process. The proposed model is exposed to different types of faults with different faults inception time, various locations, and different fault resistances. This section is discussed in three parts; the first part shed light on the faults detection and classification results. The second part deals with the dependability test. The third part evaluates the proposed scheme compared to its counterparts.

Fig. 2

Schematic diagram

3.1 Fault detection and classification test results

To verify the proposed scheme rules, consider an ABg fault occurred with fault resistance 1 kΩ created at F1 (20 km away from Bus 7). The fault case started at 1.25 s and continued for 100 ms after the fault inception. Figure 3a, b and c illustrates the current waveforms, SDI trajectories and counter output during the corresponding fault respectively. The counter is employed for computing the response time of detecting the fault condition. It will register 1 when SDI values of the faulted phases become greater than zero and keep zero when there is no fault and SDI values are zero. It is seen that, at pre-fault period, SDI trajectories have kept at zero until the fault inception, where SDI trajectories of the faulted phases jumped to the highest values and remained high along the fault period. Due to the cumulative sum process SDI value does not fall toward zero immediately even if the fault current cleared and the input current signal has become low. So, the instant that SDI has changed from zero to higher value the counter output recorded one which was happened at t = 1.254 s. Therefore, the fault is detected within 4 ms (time response) after the fault registered.

Fig. 3

ABg fault with High resistance: (a) Current waveforms, (b) SDI trajectories (c) Counter output

For more validation, the proposed algorithm has been tested under different types of faults through different circumstances. Table 1 illustrates the corresponding SDI values during Ag fault. The fault created at 20 km with different fault resistances 100 Ω, 1 kΩ, and 2kΩ respectively. The selected faults started at 1.25 s and continued for 100 ms after the fault inception. It has been seen that, SDI_A and SDI₀ are much higher than zero, and SDI_B and SDI_C are equal zero which supports the claim that the fault type is Ag fault. Furthermore, it is observed that, SDI values are decrease when the fault resistance increases. Primarily, the standard deviation estimates the extent to which the samples are far from the mean. As known, at high resistance the fault the current amplitude of the faulted phase is not large enough compared to the health phase. Therefore, the difference between the standard deviation and mean are not large enough which made SDI smaller at high resistance fault.

Table 1 SDI values during Ag at different fault resistances

Tables 2 and 3 show the corresponding SDI values during AB and ABC fault happened through different fault inception time (FIT) respectively. The fault cases created at F1 and continued for 100 ms after the fault registered. The faults cases are easy to be recognized, where SDI values of the faulted phases are much higher than zero and SDI of the healthy phases and zero sequence are zero.

Table 2 SDI values during AB occurred at different FIT

Table 3 SDI values during ABC occurred at different FIT

The results prove the independence of the proposed algorithm against the change in the fault inception time.

3.2 Dependability test

This part gives examples of testing the proposed scheme under the following faults circumstances.

3.2.1 Far-end fault

High resistance fault that occurs at the far-end is very difficult to be recognized for many algorithms. Because the current amplitude of the faulted phases are not large enough compared to the healthy phases [29]. On the other side, the fault resistance impacts the apparent impedance that seen by the distance protection relays. The reach of the relay may go out of zone and causing under-reach operation due to presence of fault resistance [25, 27]. In the proposed scheme the far-end lies at the middle of the line because the proposed scheme uses the two-terminals measurement. Figure 4 shows the impedance trajectory that seen in the conventional Mho distance scheme when an Ag fault occurs at 250 km away from sending end with fault resistance 10 Ω and 100 Ω respectively. A conventional distance protection is set for the line between Bus 7 and Bus 8 (line length 320 km). It is seen that the trajectory of Ag fault that occurred with fault resistance 10 Ω was recognized correctly within 80% protection zone, while the same Ag fault with fault resistance 100 Ω is recognized out 80% protection zone. Therefore, the fault resistance took the fault out of the coverage zone. Through this analysis, the conventional distance protection is not an accurate choice for high resistance fault that occurs at far-ends. For this case it is suggested to be integrated with the proposed scheme to raise the reliability against the far-end faults. Since the proposed scheme utilizes current measurement from both ends, the far-end lies in middle of the transmission line. Figure 5a, b and c illustrates the line current waveforms, SDI trajectories and counter output during Ag fault occurred at 320 km away from the Bus 7 with resistance 1.5kΩ. The fault case started at 1.25 s and continued for 100 ms after the fault inception. It is observed that the fault case was detected satisfactorily within 13.5 ms after the fault registered as shown in Fig. 5c.

Fig. 4

Mho trajectory during Ag fault occurred with fault resistance 10 Ω and 100 Ω respectively

Fig. 5

Ag fault occurred at far-end: (a) Current waveforms, (b) SDI trajectories (c) Counter output

3.2.2 Effect of load angle change

In this test the load angle is changed from 5⁰, 15⁰, 30⁰, − 15⁰, and − 30⁰ respectively. BCg fault simulated at 320 with fault resistance 1 kΩ is selected to perform this test. Table 4 shows the corresponding SDI values during such faults. The fault started at 1.3 s and continued for 100 ms after the fault inception. It is seen that; the faulted phases are obtained the highest SDI, while the healthy phase obtained zero. Therefore, the proposed scheme has deal correctly with faults occurred at different load angle.

Table 4 SDI values during different loading angle

3.2.3 Performance at load change in the system

This test is performed two times:

• I. load increasing: It is assumed that the system is operating at normal loading condition and another load installed in Bus 9 is switched on at t = 1.2 s. The additional MVA are equivalent 40% of the rated MVA of SM3. The line current, SDI trajectories, and output counter during such case have been shown in Fig. 6a, b and c. It is seen that SDI trajectories have kept its zero values when a sudden switching of the new load is occurred. It is evidencing that the proposed scheme criterion does not be affected by the sudden switching of the loading condition.

• II. Machine switching OFF: The proposed scheme has been tested such condition, where SM3 was switched out of the services at t = 1.2 s. Fig 6x, y and z shows the line current waveform, SDI trajectories and counter output during the corresponding test. Again, the proposed scheme criterion was not be affected by the sudden switching out of the machine. This feature proving the immunity of the proposed scheme against the sudden change in the loading condition.

Fig. 6

Sudden load change: (a) Current waveforms, (b) SDI trajectories (c) Counter output during 40% increase in SM3 MVA, (x) Current waveforms, (y) SDI trajectories (z) Counter output during switching OFF of SM3

3.2.4 Effect of CT saturation

Faults occur nearby the terminals are carrying a high risk to the electric equipment. It may cause CTs saturation which increase the possibility of incorrect operation. Furthermore, nearby faults generate large fault currents, if not cleared promptly, it may endanger the entire electric power system. Therefore, it requires a fast and reliable protection system to limit equipment damage [25]. Herein, the close-in fault to the sending end is selected to perform the CT test. All the tests in this paper are performed by using the secondary current of CTs with turn ratio 1000/5, burden 5 Ω, installed in the sending end and receiving. Fig. 7a, b and c shows the current waveforms, SDI trajectories, and counter output during an ABCg fault that occurred at 8 km away from the Bus 7. SDI trajectories of the three-phases started taking high values at 1.502 which means the fault condition is detected after 2 ms from the fault inception. This feature reflecting the effectiveness of the proposed algorithm against the nearby faults.

Fig. 7

Fault happened nearby terminal, (a) Current waveforms, (b) SDI trajectories (c) counter output

3.2.5 Impact of the bad signaling

Bad signals or signal distortion can occur due to noise interference with the original signals. Bad signaling tests are performed by injecting White Gaussian Noise (WGN) with noise signal ratio (SNR) 25 dB in the current signal of the remote terminal. BCg fault is selected to perform the test, where phase A and phase C contaminated with noise and phase B remain free of noise. The fault case is created at 320 km with a resistance 1 kΩ. The fault case started at 1.15 s and continued for 50 ms after the fault inception. Figure 8a, b and c shows the current waveforms, SDI trajectories and counter output during such test. The fault condition is easy to be identified, where the SDI trajectories of the faulted phases started getting high values after the fault inception while SDI trajectory of the healthy phase has kept in zero. Additionally, the fault was detected within 12 ms after the fault inception.

Fig. 8

Fault occurred at the presence of Noise, (a) Current waveforms, (b) SDI trajectories (c) counter output

As known, the smaller SNR level gives higher distortion level. As a result, the corrupted signals moving away from its pure sinusoidal and vice versa. In order to show the impact of SNR levels, the same BCg fault is repeated with different SNR levels. Table 5 contains the corresponding SDI values during such condition. It is observed that, the proposed scheme performed appropriately with noise interference up 20 dB which reflecting the immunity of the proposed scheme against the noises.

Table 5 SDI values during ABg fault at different SNR

3.2.6 Effect of sampling frequencies

The proposed scheme used 4 kHz as sampling rate at 50 Hz which gives 80 samples per cycle. Table 6 shows the SDI values during ABg faults occurred at different sampling rate. The fault cases are carried at 320 km with fault the resistance 1 kΩ. It is started at 1.15 s and continued or 100 ms after the fault registered. Higher sampling rate makes the fault detector act faster because the number of samples per cycle is larger [30]. Since the proposed scheme using the standard deviation which depends on the mean of the data, then an accurate mean will be provided at higher sampling frequencies (large number of samples per cycle). However, high sampling frequencies may require large storage capacities. Therefore, 4 kHz is the best choice for the proposed scheme.

Table 6 SDI values during different sampling rate

3.2.7 Effect of data latency of remote terminal

The proposed algorithm can be categorized as a unit protection because of using data from two-terminals. The reliability of such scheme relies on the trustworthiness of the communication system and its cost [31]. Therefore, it is important to test such schemes if there is a delay in the data that collected from the remote terminal. The proposed scheme has been tested when there was a delay occurred to the remote data. An Ag fault that occurred at 320 with fault resistance 500 Ω is selected to perform the test, it is started at 1.25 s and continued for 100 ms. Figure 9a, b and c shows the current waveforms, SDI trajectory, and counter output during the normal case (without delay in the remote data). Figure 9x, y and z shows the current waveforms, SDI trajectory, and counter output when the remote data has delayed 10 ms from the original inception. I_rA denote the remote current, I_sA denotes the sending end current, and I_A denote the employed current which results due to the sum of sending and remote current. It is seen that the when the current signals were delayed 10 ms the proposed scheme still can work satisfactorily. This situation confirmed the reliability of the proposed scheme against the data latency of remote terminals up 10 ms.

Fig. 9

Performance during remote data latency: (a) Current waveforms, (b) SDI trajectories (c) Counter output at ordinary case (before the delay in the current of the remote terminal). (x) Current waveforms, (y) SDI trajectories (z) Counter output after 10 ms delay of the remote-terminal current (I_rA) from its original moments

3.2.8 Impact of series compensation presence

Fixed series compensation is often used for enhancing a power transmission line performance. However, a lot of challenges will encounter the protection system. The main impact of series compensation cab be summarized in the following:

• Continuous change in the impedance seen by the relays due to the operation of the series capacitors. At high-current fault condition the voltage across the capacitor increases to a truly high value, then the MOV will be conducted, and the impedance of MOV is only be added up to the total impedance that seen by the distance relay. In low-current fault condition; the MOV remained in its high impedance state, then the parallel impedance of the sets will be added to the total impedance that seen by the distance relay.

• Voltage inversion: it is a variation of 180 degrees in the voltage phase, it can occur during a fault that happens near-series capacitor if the impedance from relay location to the fault is capacitive rather than inductive

• Current inversion: it occurs when, the equivalent circuit of the system at one side of the fault is more capacitive, and the equivalent system at the other side fault is inductive, where the current seems to flow out of the line at one terminal. The high-low faults current could create a current inversion.

• The inclusion of series compensation may magnify the unbalance impedance in the system

Therefore, occurring faults at far-end with high resistance, close-in fault with high resistance at the presence of series capacitor’s units represent challenges to many algorithms of fault identification in power transmission line. The proposed scheme has been tested under the presence of series capacitors (193.9 μf) installed at 320 km away from Bus 7. An ABg fault is selected to perform the test, it has been simulated several times front and behind the series capacitors units (SCU). The fault cases are carried out with fault resistance 1 kΩ. Table 7 provides the corresponding SDI results during such faults. The fault cases started at 1.25 s and continued for 100 ms after the fault inception. All fault scenarios were detected satisfactorily which one can conclude that the proposed scheme has a good performance against the fault that happens in the presence of series capacitors.

Table 7 SDI values during ABg faults with high resistance at the presence of series capacitors

3.3 Comparison with other techniques

The principle of the comparison based on the performance of dealing with the far-end fault with HRF and the response time. The proposed scheme has obtained better performance from the view of high fault resistance compared to the conventional cumulative approaches and moving windows that reported in [14, 25, 32]. The schemes [18, 19] do not mention the time response. Therefore, the proposed algorithm has marked them in term of high resistance fault. Table 8 shows the comparative assessment with similar schemes.

Table 8 Comparative assessment with previous work

4 Conclusions

This paper presented a simple scheme for detecting and classifying a high resistance fault in power transmission line. The proposed scheme employed the standard deviation of the current signals that measured from both terminals with a cumulative approach to swell the fault feature during high resistance fault. The output is named as standard deviation indices (SDI) and used as a tool for performing the high resistance fault. The proposed scheme was applied to the different fault’s scenarios such as different locations, different resistances and different faults inceptions time. As well as faults occurred under noise condition, various load angles, different sampling frequencies and faults occurred at the presence of series capacitance. The CT saturation and sudden loading condition change are also discussed. For all possible fault’s scenarios, the proposed algorithm showed a good performance and achieved its targets with remarkable time response. In general, it possible to consider that the proposed scheme is an improvement of the cumulative techniques to be more reliable to resistance faults. Finally, the proposed algorithm is characterized by its simplicity and reasonableness. It is recommended to be integrated with conventional distance protection to enhance the performance of detecting the far-end fault with high resistance.

Appendix

Table 9 IEEE 9 Bus Parameters